Curriculum in preparation

Build a complete PCIe UVM testbench from scratch. Covers PCIe agent architecture, TLP/DLLP generation, link training sequences, error injection, protocol checkers, coverage models, and regression methodology targeting PCIe endpoint and root complex implementations.

Curriculum in preparation

Prepare for PCIe Gen6 – the next-generation 64GT/s interconnect using PAM4 signalling. Covers Gen6 FLIT-based encoding, PAM4 vs NRZ, L0p power state, FEC in Gen6, and CXL 3.0 co-evolution. Ideal for engineers at the frontier of high-speed interconnect design.

Curriculum in preparation

Deep-dive into PCIe Gen5 at 32GT/s. Covers Gen5 physical layer improvements, signal integrity challenges, equalization, FEC, PCIe 5.0 spec changes, and interaction with CXL 2.0. Targeted at DV and hardware engineers in data centre and AI accelerator companies.

Curriculum in preparation

Learn PCIe Gen4 protocol architecture and verification. Covers PCIe layered architecture, Gen4 electrical specifications, LTSSM link training, TLP/DLLP packet structures, flow control, and PCIe Gen4 DV methodology using SystemVerilog and UVM-based PCIe VIP.