Curriculum in preparation

Design a complete RISC-V processor from scratch. Covers RISC-V ISA (RV32I/RV64I), 5-stage pipeline design, hazard detection, memory subsystem, interrupt handling, and SoC integration. Final project synthesises a full RISC-V core on FPGA and targets a standard cell library for ASIC tape-out.

Available now · Self-paced

Understand memory compiler design and integration for ASIC chips. Covers SRAM architecture, memory compiler configuration, timing model interpretation, wrapper RTL design, memory BIST integration, and memory redundancy. Hands-on use of ARM Memory Compiler and Cadence Genus memory integration flows.

Curriculum in preparation

Learn how constraints drive RTL synthesis and physical design closure. Covers full SDC constraint creation, false path and multi-cycle path identification, clock definitions, I/O delay constraints, and constraint validation. Bridges the gap between RTL design and Physical Design handoff – a critical

Available now · Self-paced

Master FIFO design for synchronous and asynchronous clock domains. Covers FIFO depth estimation, pointer arithmetic, Gray code CDC FIFOs, almost-full/empty flags, burst-mode FIFOs, and synthesis-safe implementation. Includes formal verification of CDC properties and integration into AXI streaming in

Available now · Self-paced

Learn professional RTL design methodology for ASIC chips. Covers microarchitecture planning, pipeline design, arbitration logic, CDC-awareness, lint-clean RTL, synthesis optimisation, and design-for-verification practices. Projects include designing a complete AXI-based SoC subsystem block.

Available now · Self-paced

Become proficient in Verilog for ASIC and FPGA design. Covers all Verilog constructs, synthesis-aware RTL coding, parameterisation, always blocks, generate statements, and testbench writing. Projects design arithmetic units, FIFOs, and state machines targeting real synthesis with Synopsys DC and Cad