Courses

UCIe Protocol Training

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Learn UCIe – the open standard for chiplet-based die-to-die interconnects. Covers UCIe physical and protocol layers, die-to-die adapter architecture, advanced and standard packaging form factors, and UCIe IP integration strategy.

HBM3 Protocol Training

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Learn HBM3 – the ultra-high-bandwidth memory used in AI accelerators and GPUs. Covers HBM3 architecture, 3D stacking (TSV), wide 1024-bit interface, refresh management, thermal design, and HBM3 PHY interface. Essential for AI chips, GPUs, and network processors.

CXL Protocol Training

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Master CXL – the emerging coherent interconnect for CPU-accelerator-memory systems. Covers CXL 1.1/2.0/3.0 specifications, CXL.io, CXL.cache, CXL.mem, and CXL switch topology. Essential for AI accelerator, HPC, and data centre SoC engineers.

NVMe Training

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Learn NVMe (NVM Express) – the high-performance storage protocol over PCIe. Covers NVMe command set, submission/completion queue pairs, admin commands, NVMe namespaces, power management, and NVMe-oF with NVMe controller DV methodology.

DisplayPort Protocol Training

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Learn the DisplayPort protocol for high-resolution display interfaces. Covers DP 1.4 and DP 2.0 (UHBR) architecture, main link and AUX channel, link training, MST, HDCP 2.3, DSC, and USB-C integration. Targeted at multimedia SoC and GPU design engineers.

UART Training

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Learn UART – the most fundamental serial communication protocol. Covers UART framing (start/stop/parity bits), baud rate generation, RS232/RS485 levels, FIFO-buffered UART design, flow control (RTS/CTS), and UART controller RTL implementation.