Available now · Self-paced

Become proficient in Verilog for ASIC and FPGA design. Covers all Verilog constructs, synthesis-aware RTL coding, parameterisation, always blocks, generate statements, and testbench writing. Projects design arithmetic units, FIFOs, and state machines targeting real synthesis with Synopsys DC and Cad

Curriculum in preparation

Start your RTL journey with Hardware Description Languages. Introduces Verilog and VHDL syntax, module hierarchy, data types, concurrent vs sequential statements, simulation basics, and synthesis-friendly coding styles. Perfect for ECE graduates and IT professionals transitioning into VLSI/semicondu

Curriculum in preparation

Learn systematic timing closure methodology for complex ASIC designs. Covers setup and hold ECOs, buffer/inverter insertion, cell sizing, clock skew exploitation, useful skew, and multi-corner timing closure strategies. Includes real ECO sessions on industrial-grade designs with 1000+ violations acr

Curriculum in preparation

Go beyond basic STA with advanced timing analysis. Covers AOCV/POCV statistical timing, CCSN/ECSM cell models, MMMC setup, advanced clock network analysis, hold margin management at advanced nodes, and ECO-driven timing closure. Essential for STA engineers working at 7nm and below.

Curriculum in preparation

Analyse and fix signal and power integrity issues in high-speed VLSI designs. Covers crosstalk noise, glitch analysis, transmission line effects, aggressor-victim coupling, SI-driven routing rules, and co-simulation of SI/PI using Cadence Sigrity and Innovus SI flows.

Curriculum in preparation

Design robust Power Delivery Networks (PDN) for high-performance ICs. Covers PDN impedance analysis, power mesh design, decoupling capacitor placement, bump assignment for flip-chip designs, and PDN simulation using Cadence Voltus. Includes advanced topics on package-chip co-design and chiplet PDN c

Curriculum in preparation

Tackle advanced routing challenges in modern ASIC designs. Covers global and detail routing algorithms, congestion analysis and mitigation, DRC-clean routing strategies, shield routing for sensitive nets, and post-route ECOs. Project-based course using Cadence Innovus Nanoroute on a real hierarchica

Curriculum in preparation

Design power-efficient ICs with advanced low-power techniques. Covers clock gating, power gating, multi-voltage domain design, UPF/CPF power intent, DVFS strategies, retention flops, isolation cells, and level shifters. Essential for engineers working on mobile SoCs, automotive ICs, and IoT chip des

Curriculum in preparation

Master floorplanning and chip-level planning for ASIC design. Learn die size estimation, aspect ratio selection, macro placement strategies, power ring and stripe design, IO planning, and hierarchical floorplanning techniques. Uses Cadence Innovus with real SoC hierarchical designs for practical ses