Courses
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Learn the fundamentals of DFT for ASIC and SoC designs. Covers stuck-at and transition fault models, scan chain insertion, test compression (EDT), boundary scan (JTAG/IEEE 1149.1), ATPG fundamentals, and DFT sign-off methodology. Uses Synopsys DFT Compiler and Mentor Tessent flows.
0 Lessons
Hours
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Design complete Power Management ICs (PMIC). Covers LDO regulator design, buck and boost DC-DC converter architectures, bandgap references, charge pumps, battery management circuits, and multi-rail PMIC integration. Design and simulate complete PMIC blocks using Cadence Virtuoso with automotive and
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Design RF circuits in standard CMOS technology. Covers LNA, mixer, VCO, and PA design; S-parameter analysis; noise figure optimisation; impedance matching; and RF layout strategies. Uses Cadence Virtuoso with RF PDKs for simulation and layout. Targeted at wireless SoC, IoT, and RF IC design engineer
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Design robust I/O pads and high-speed serial interfaces for modern SoCs. Covers ESD protection circuits, IO pad design, SERDES architecture, LVDS/differential signalling, DDR IO training circuits, and impedance-controlled IO using IBIS models and ADS simulation.
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Hours
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Advanced custom layout techniques for high-performance analog and RF ICs. Covers RF layout for inductors and capacitors, deep submicron layout challenges, FinFET layout rules, advanced matching, thermal considerations, and tape-out preparation for 28nm/16nm technology nodes using Cadence Virtuoso.
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Hours
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Master Analog/Mixed-Signal (AMS) design for SoC integration. Covers ADC and DAC architectures, PLL design and analysis, bandgap references, LDO regulators, and analog-digital interface challenges. AMS co-simulation using Cadence Virtuoso AMS with Verilog-A models bridges the gap between analog and d
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Hours
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Design CMOS analog circuits from first principles using Cadence Spectre. Covers biasing, current mirrors, differential pairs, single-stage and multi-stage amplifiers, op-amp design, bandwidth, stability, and noise analysis. Simulation on real technology PDKs. Essential for analog IC designers and mi
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Hours
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Learn professional analog IC layout techniques using Cadence Virtuoso. Covers MOSFET layout, matching techniques, common centroid structures, guard rings, shielding, ESD protection layout, DRC/LVS clean design, and parasitic-aware layout optimisation. Targeted at engineers seeking analog, mixed-sign
26 Lessons
14:37:06 Hours
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Apply formal verification to prove design correctness mathematically. Covers SVA property writing, model checking theory, assume-guarantee reasoning, and tool-driven formal apps (connectivity, CDC, datapath) using Cadence JasperGold and Synopsys VC Formal. Real sign-off projects on bus interface and
7 Lessons
03:40:23 Hours