Courses

Clock Domain Crossing (CDC) Training

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Master CDC analysis and verification. Covers metastability, synchroniser design, multi-bit CDC paths, gray code FIFOs, CDC waivers, and formal CDC sign-off using SpyGlass and Mentor Questa CDC. Critical for SoC designs with multiple clock domains – a leading cause of silicon bugs.

Testbench Development

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Learn structured testbench development for VLSI designs. Covers testbench architecture, stimulus generation, self-checking testbenches, assertion-based verification, functional coverage planning, and verification closure methodology. Uses Synopsys VCS and Cadence Xcelium simulators with real ASIC de

UVM

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Master UVM – the industry-standard ASIC verification methodology. Build a complete UVM testbench from scratch: agents, drivers, monitors, scoreboards, coverage collectors, and virtual sequences. Covers RAL, callback hooks, factory overrides, and coverage closure. Projects target AXI and PCIe protoco

System Verilog

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Learn SystemVerilog for design verification with OOP methodology. Covers SV data types, interfaces, clocking blocks, SVA assertions, functional coverage, and constraint-random stimulus. Essential prerequisite for UVM and used across all ASIC verification teams globally.

RISC-V Architecture & Design

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Design a complete RISC-V processor from scratch. Covers RISC-V ISA (RV32I/RV64I), 5-stage pipeline design, hazard detection, memory subsystem, interrupt handling, and SoC integration. Final project synthesises a full RISC-V core on FPGA and targets a standard cell library for ASIC tape-out.

Memory Compiler Design

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Understand memory compiler design and integration for ASIC chips. Covers SRAM architecture, memory compiler configuration, timing model interpretation, wrapper RTL design, memory BIST integration, and memory redundancy. Hands-on use of ARM Memory Compiler and Cadence Genus memory integration flows.

Constraint-Driven Design

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Learn how constraints drive RTL synthesis and physical design closure. Covers full SDC constraint creation, false path and multi-cycle path identification, clock definitions, I/O delay constraints, and constraint validation. Bridges the gap between RTL design and Physical Design handoff – a critical

Advanced FIFO Design

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Master FIFO design for synchronous and asynchronous clock domains. Covers FIFO depth estimation, pointer arithmetic, Gray code CDC FIFOs, almost-full/empty flags, burst-mode FIFOs, and synthesis-safe implementation. Includes formal verification of CDC properties and integration into AXI streaming in

RTL Design Course

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Learn professional RTL design methodology for ASIC chips. Covers microarchitecture planning, pipeline design, arbitration logic, CDC-awareness, lint-clean RTL, synthesis optimisation, and design-for-verification practices. Projects include designing a complete AXI-based SoC subsystem block.