Courses

AMBA - AXI Protocol Training

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Learn the AMBA AXI protocol – the backbone of modern SoC designs. Covers AXI4 read/write channels, handshaking, burst types, AXI-Lite for register access, AXI-Stream for data streaming, and AXI interconnect topology. Includes UVM-based AXI verification environment development for real SoC subsystems

PCIe Testbench (TB) Development Training

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Build a complete PCIe UVM testbench from scratch. Covers PCIe agent architecture, TLP/DLLP generation, link training sequences, error injection, protocol checkers, coverage models, and regression methodology targeting PCIe endpoint and root complex implementations.

PCIe Gen6 Training

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Prepare for PCIe Gen6 – the next-generation 64GT/s interconnect using PAM4 signalling. Covers Gen6 FLIT-based encoding, PAM4 vs NRZ, L0p power state, FEC in Gen6, and CXL 3.0 co-evolution. Ideal for engineers at the frontier of high-speed interconnect design.

PCIe Gen5 Training

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Deep-dive into PCIe Gen5 at 32GT/s. Covers Gen5 physical layer improvements, signal integrity challenges, equalization, FEC, PCIe 5.0 spec changes, and interaction with CXL 2.0. Targeted at DV and hardware engineers in data centre and AI accelerator companies.

PCIe Gen4 Training

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Learn PCIe Gen4 protocol architecture and verification. Covers PCIe layered architecture, Gen4 electrical specifications, LTSSM link training, TLP/DLLP packet structures, flow control, and PCIe Gen4 DV methodology using SystemVerilog and UVM-based PCIe VIP.

Design and Verification Course

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The complete package for engineers targeting both Design and Verification roles. Covers Verilog RTL design, SystemVerilog, UVM testbench construction, simulation-based verification, and synthesis handoff. Designed for final-year students and career-switchers seeking full-stack VLSI competency with a

BIST – Memory & Logic

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Design and implement BIST structures for memories and logic. Covers MBIST controller design, March test algorithms, memory repair, LBIST architectures, LFSR pattern generators, MISR compactors, and at-speed BIST for automotive ISO 26262 requirements. Uses Mentor Tessent MBIST flow.

ATPG & Test Pattern Generation

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Generate high-quality test patterns using ATPG for maximum fault coverage. Covers stuck-at, transition, and path delay fault models, fault simulation, ATPG pattern optimisation, diagnostic patterns, and tester-ready pattern export. Uses Synopsys TetraMAX and Mentor Tessent on real SoC designs.

Scan Chain Insertion & Compression

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Master scan chain design and test compression. Covers scan flip-flop selection, scan enable routing, EDT/OPMISR compression, scan reordering, X-bounding, and test data volume reduction. Hands-on with Synopsys DFT Compiler and Mentor Tessent for real ASIC scan insertion and ATPG pattern generation.