Courses

RISC-V Embedded Software Development

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Develop embedded software for RISC-V processors. Covers RISC-V toolchain setup, bare-metal startup code, privilege levels (M/S/U mode), OpenSBI, RISC-V Linux bring-up, and RISC-V assembly. Labs use SiFive HiFive and ESP32-C3 hardware.

Device Drivers and BSP Development

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Learn to write device drivers and Board Support Packages (BSP) for embedded Linux and bare-metal systems. Covers Linux kernel driver model, platform drivers, character and block device drivers, DTS authoring, I2C/SPI/GPIO driver implementation, and BSP bring-up for custom hardware.

ARM Cortex-M Architecture and Programming

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Deep-dive into ARM Cortex-M processor architecture and programming. Covers Cortex-M4/M33 pipeline, NVIC, SysTick, MPU, Thumb-2 instruction set, exception handling, low-power modes, and CMSIS usage. Engineers write optimised firmware exploiting Cortex-M hardware features for IoT and embedded products

RTOS Fundamentals FreeRTOS Zephyr

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Master Real-Time Operating Systems for embedded product development. Covers preemption, priority inversion, deadlock, FreeRTOS task/queue/semaphore/mutex APIs, Zephyr RTOS kernel, device tree, and inter-task communication. Projects build multi-threaded firmware on STM32 and Nordic nRF platforms.

Embedded C and Bare-Metal Programming

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Learn embedded C programming for bare-metal microcontroller development. Covers startup code, linker scripts, GPIO/interrupt/timer programming, memory-mapped I/O, bitfield manipulation, and peripheral driver development on ARM Cortex-M (STM32) and RISC-V platforms.

Hardware Software Co-design for AI SoCs

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Design AI SoCs with aligned hardware and software stacks. Covers AI SoC architecture trade-offs, compiler (TVM/MLIR) to hardware mapping, driver and runtime design, operator library optimisation, and full-stack performance profiling for next-generation AI inference and training chips.

LLM and GenAI Integration in EDA Flows

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Leverage LLMs and Generative AI in EDA and VLSI workflows. Covers RTL code generation with LLMs, AI-assisted DRC violation explanation, automated constraint generation, LLM-based verification plan writing, and responsible AI use in semiconductor design. Hands-on with Claude, GPT-4, Cadence AI, and S

On-Chip ML Inference Optimisation

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Optimise ML inference performance on custom AI chips. Covers memory hierarchy design for ML (on-chip SRAM, HBM, DRAM), weight compression and caching strategies, operator fusion, pipeline utilisation, data reuse analysis, and power-performance trade-offs on NPU simulators.

AI and ML for Verification Coverage-Driven

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Apply AI/ML techniques to accelerate functional verification coverage closure. Covers ML-based stimulus generation, coverage gap analysis using clustering, reinforcement learning for constrained-random tests, and ML-driven regression optimisation with Cadence vManager AI and JasperGold AI-driven for