Courses

AI-Assisted Physical Design and CTS

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Learn how AI/ML is revolutionising Physical Design flows. Covers ML-based placement optimisation, AI-driven clock tree synthesis, reinforcement learning for routing, predictive congestion analysis, and AI-powered timing closure using Cadence Cerebrus and Synopsys DSO.ai.

AI Accelerator Architecture NPU TPU

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Architect AI accelerators (NPU/TPU) for ML inference and training. Covers systolic array architecture, dataflow analysis (weight stationary, output stationary), GEMM/convolution hardware mapping, on-chip SRAM sizing, memory bandwidth analysis, and tiling strategies. Projects design and simulate a si

Neural Network Inference on Edge Chips

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Deploy neural network inference on edge AI chips and embedded platforms. Covers quantisation (INT8/INT4), model pruning, TensorFlow Lite, ONNX runtime, NPU operator mapping, memory bandwidth optimisation, and latency profiling. Hands-on deployment on ARM Ethos NPU, Raspberry Pi 5, and custom edge AI

ML Fundamentals for Hardware Engineers

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Bridge the gap between machine learning and hardware engineering. Covers ML fundamentals (linear models, neural networks, CNNs, transformers), training vs inference, quantisation, pruning, and how ML workloads map to hardware. Designed for VLSI, FPGA, and embedded engineers who need AI/ML literacy f

Partial Reconfiguration on FPGA

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Learn FPGA Partial Reconfiguration / Dynamic Function Exchange (DFX) for run-time hardware flexibility. Covers static vs reconfigurable partition design, decoupling logic, partial bitstream generation, ICAP interface, and PR use cases in software-defined radio and adaptive computing.

PCIe on FPGA Design and Verification

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Implement and verify PCIe on FPGA using vendor IP cores. Covers Xilinx PCIe IP configuration, BAR design, DMA controller integration, interrupt handling, PCIe compliance testing, and in-system debug with PCIe protocol analysers. Hands-on DMA engine implementation on Xilinx UltraScale+ hardware.

FPGA-Based Prototyping for ASICs

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Learn FPGA-based ASIC prototyping for pre-silicon software validation. Covers FPGA partitioning strategies, TDM for inter-FPGA connectivity, prototype bring-up methodology, debug insertion, and SW/FW validation on FPGA prototypes using Synopsys HAPS and Xilinx VU19P platforms.

High-Level Synthesis HLS with Vitis

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Accelerate hardware design with High-Level Synthesis using Xilinx Vitis HLS. Covers C/C++ to RTL synthesis, pipeline and dataflow optimisation pragmas, memory partitioning, AXI interface synthesis, and co-simulation. Projects implement ML inference accelerators and DSP kernels for FPGA acceleration.

FPGA Timing Constraints and Closure

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Master FPGA timing constraint methodology for clean timing closure. Covers XDC constraint creation, CDC constraint handling, I/O timing, multi-clock designs, and timing closure debugging in Vivado Timing Analyser. Directly applicable to real-product FPGA designs.